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this is information on a product in full production. august 2014 docid026211 rev 3 1/63 a6986 38 v 2 a synchronous step-down switching regulator with 30 a quiescent current datasheet - production data features ? aecq100 qualification ? 2 a dc output current ? 4 v to 38 v operating input voltage ? low consumption mode or low noise mode ? 30 a iq at light load (lcm v out = 3.3 v) ? 8 a i q-shtdwn ? adjustable f sw (250 khz - 2 mhz) ? output voltage adjustable from 0.85 v to v in ? embedded output voltage supervisor ? synchronization ? adjustable soft-start time ? internal current limiting ? overvoltage protection ? output voltage sequencing ? peak current mode architecture ? r dson hs = 180 m ? , r dson ls = 110 m ? ? thermal shutdown applications ? designed for automotive systems ? battery powered applications ? car body applications (lcm) ? car audio and low noise applications (lnm) description the a6986 device is a step-down monolithic switching regulator able to deliver up to 2 a dc. the output voltage adju stability ranges from 0.85 v to vin. the 100% duty cycle capability and the wide input voltage range meet the cold crank and load dump specifications for automotive systems. the ?low consumption mode? (lcm) is designed for applications active during car parking, so it maximizes the efficiency at light load with controlled output voltage ripple. the ?low noise mode? (lnm) makes the switching frequency constant and minimizes the output voltage ripple overload current range, meeting the low noise application specif ication like car audio. the output voltage supervisor manages the reset phase for any digital load (c, fpga.). the rst open collector output can also implement output voltage sequencing during the power-up phase. the synchronous rectification, designed for high efficiency at medium - heavy load, and the high switching frequency capab ility make the size of the application compact. pulse by pulse current sensing on both power elements implements an effective constant current protection. htssop16 (r th = 40 c/w) www.st.com
contents a6986 2/63 docid026211 rev 3 contents 1 application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.4 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.5 esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 datasheet parameters over the temperatur e range . . . . . . . . . . . . . . . 13 5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 power supply and voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 switchover feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2 voltages monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3 soft-start and inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3.1 ratiometric startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.3.2 output voltage sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.4 error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.5 light load operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.5.1 low noise mode (lnm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.5.2 low consumption mode (lcm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.6 switchover feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.6.1 lcm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.6.2 lnm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.7 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 ocp and switchover feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.8 overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5.9 thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
docid026211 rev 3 3/63 a6986 contents 63 6 closing the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1 g co (s) control to output transfer function . . . . . . . . . . . . . . . . . . . . . . . . 32 6.2 error amplifier compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.3 voltage divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.4 total loop gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.5 compensation network design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7 application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.1 output voltage adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.2 switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.3 mlf pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.4 voltage supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.5 synchronization (lnm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.6 design of the power components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.6.1 input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.6.2 inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.6.3 output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8 application board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9 efficiency curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 11 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
application schematic a6986 4/63 docid026211 rev 3 1 application schematic figure 1. application schematic 6ljqdo*1' 3:5*1' 3:5*1' & q) 9287 9287 & 9 & $ 9%,$6 567 9&& 66,1+ 6<1&+ )6: 0/) &203 '(/$< )% 6*1' 3*1' 3*1' /; /; 9,1 (3 5 5 *1' *1' & q) & 9 & *1' *1' / / & & & q) 5 5 5 5 & s) 9,1 9,1 5 5 $09
docid026211 rev 3 5/63 a6986 pin settings 63 2 pin settings 2.1 pin connection figure 2. pin connection (top view) 2.2 pin description 9%,$6 9,1 /; /; 3*1' 3*1' 6*1' )% 567 9&& 66,1+ 6<1&+ )6: 0/) &203 '(/$< (;326(' 3$'72 6*1' table 1. pin description no. pin description 1rst the rst open collector output is driven low when th e output voltage is out of regulation. the rst is released after an adjustable time delay once the output voltage is over the active delay threshold. 2vcc connect a ceramic capacitor ( 470 nf) to filter internal voltage reference. this pin supplies the embedded analog circuitry. 3 ss/inh an open collector stage can disable the device clamping this pin to gnd (inh mode). an internal current generator (2 ? a typ.) charges the external capaci tor to implement the soft-start. 4 synch master / slave synchronization 5fsw a pull up resistor (e24 series only) to vcc or pull down to gnd selects the switching frequency. pinstrapping is active only before the soft-sta rt phase to minimize the ic consumption. 6mlf a pull up resistor (e24 series only) to vcc or pull down to gnd selects the low noise mode/low consumption mode and the active rst threshold. pi nstrapping is active only before the soft-start phase to minimize the ic consumption. 7 comp output of the error amplifier. the designed compensation network is connected at this pin. 8delay an external capacitor connected at this pin sets the time delay to assert the rising edge of the rst o.c. after the output voltage is over the reset th reshold. if this pin is left floating, rst is like a power good. 9 fb inverting input of the error amplifier 10 sgnd signal gnd 11 pgnd power gnd
pin settings a6986 6/63 docid026211 rev 3 2.3 maximum ratings stressing the device ab ove the rating listed in table 2: absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions may affect device reliability. 12 pgnd power gnd 13 lx switching node 14 lx switching node 15 vin dc input voltage 16 v bias typically connected to the regulat ed output voltage. an external volt age reference can be used to supply part of the analog circuitry to increase th e efficiency at light load. connect to gnd if not used. - e. p. exposed pad must be connected to sgnd table 1. pin description (continued) no. pin description table 2. absolute maximum ratings symbol description min. max. unit v in see table 1 40 v delay -0.3 v cc + 0.3 v pgnd sgnd - 0.3 sgnd + 0.3 v sgnd v v cc -0.3 (v in + 0.3) or (max. 4) v ss / inh -0.3 v in + 0.3 v mlf -0.3 v cc + 0.3 v comp -0.3 v cc + 0.3 v fb -0.3 v cc + 0.3 v fsw -0.3 v cc + 0.3 v synch -0.3 v in + 0.3 v v bias -0.3 (v in + 0.3) or (max. 6) v rst -0.3 v in + 0.3 v lx -0.3 v in + 0.3 v t j operating temperature range -40 150 c t stg storage temperature range -65 to 150 c t lead lead temperature (soldering 10 sec.) 260 c i hs , i ls high-side / low-side switch current 2 a
docid026211 rev 3 7/63 a6986 pin settings 63 2.4 thermal data 2.5 esd protection table 3. thermal data symbol parameter value unit r th ja thermal resistance junction ambi ent (device soldered on the stmicroelectronics ? demonstration board) 40 c/w table 4. esd protection symbol test condition value unit esd hbm 2 kv mm 150 v cdm 500 v
electrical characteristics a6986 8/63 docid026211 rev 3 3 electrical characteristics t j = -40 to 135 c, v in = 12 v unless otherwise specified. table 5. electrical characteristics symbol parameter test condition note min. typ. max. unit v in operating input voltage range 4 38 v v inh v cc uvlo rising threshold 2.7 3.5 v inl v cc uvlo falling threshold 2.5 3.5 i pk peak current limit duty cycle < 40% 2.6 a duty cycle = 100% closed loop operation 2.1 i vy valley current limit 2.7 i skip skip current limit (1) 0.6 0.8 i vy_snk reverse current limit lnm or v out overvoltage 0.5 1 2 r dson hs high-side rdson i sw = 1 a 0.18 0.36 0 ? r dson ls low-side rdson i sw = 1 a 0.15 0.30 0 f sw selected switching frequen cy fsw pinstrapping before ss see table 6: f sw selection i fsw fsw biasing current ss ended 0 500 na lcm/lnm low noise mode / low consumption mode selection mlf pinstrapping before ss see table 7: lnm / lcm selection on page 12 i mlf mlf biasing current ss ended 0 500 na d duty cycle (2) 0100% t on min minimum on time 100 ns vcc regulator v cc ldo output voltage v bias = gnd (no switchover) 2.9 3.3 3.6 v v bias = 5 v (switchover) 2.9 3.3 3.6 swo v bias threshold switch internal supply from v in to v bias 2.85 3.2 switch internal supply from v bias to v in 2.8 3.15
docid026211 rev 3 9/63 a6986 electrical characteristics 63 power consumption i shtdwn shutdown current from v in v ss/inh = gnd 4 8 15 ? a i q opvin quiescent current from v in lcm - swo v ref < v fb < v ovp (sleep) v bias = 3.3 v (3) 41015 ? a lcm - no swo v ref < v fb < v ovp (sleep) v bias = gnd (3) 35 70 120 lnm - swo v fb = gnd (no sleep) v bias = 3.3 v 0.5 1.5 5 ma lnm - no swo v fb = gnd (no sleep) v bias = gnd 22.86 i q opvbias quiescent current from v bias lcm - swo v ref < v fb < v ovp (sleep) v bias = 3.3 v (3) 20 50 115 ? a lnm - swo v fb = gnd (no sleep) v bias = 3.3 v 0.5 1.2 5 ma soft-start v inh vss threshold ss rising 200 460 700 mv v inh hyst vss hysteresis 60 i ss ch c ss charging current v ss < v inh or t < t ss setup or v ea+ > v fb (2) 1 ? a t > t ss setup and v ea+ < v fb (2) 4 v ss clmp ss discharge voltage v cc < v cch or t < t ss setup or thermal fail 855 900 945 mv v ss start start of internal error amplifier ramp 0.995 1.1 1.15 0 v ss gain ss/inh to internal error amplifier gain 3 v ss end ss/inh voltage at the end of ss phase 2.5 3.6 v table 5. electrical ch aracteristics (continued) symbol parameter test condition note min. typ. max. unit
electrical characteristics a6986 10/63 docid026211 rev 3 error amplifier v fb voltage feedback 0.841 0.85 0.85 9 v i fb fb biasing current 50 500 na g m transconductance 90 155 210 ? s (4) 70 155 210 a v error amplifier gain (2) 100 db i comp ea output current capability 6 12 25 ? a (4) 4 inner current loop g cs current sense transconductance (v comp to inductor current gain) ipk = 1 a (5) 2.5 a/v slope compensation (5) 0.4 0.75 1.0 a overvoltage protection v ovp overvoltage trip (v ovp /v ref ) 1.15 1.2 1.25 v ovp hyst overvoltage hysteresis 1 2 6 % synchronization (fan out: 6 slave devices typ.) f syn min synchronization frequency lnm; f sw = vcc 266.5 khz v syn th synch input threshold lnm, synch rising 0.70 1.2 v i syn synch pulldown current lnm, v syn = 1.2 v 0.7 ma v syn out high level output lnm, 5 ma sinking load 1.40 v low level output lnm, 0.7 ma sourcing load 0.6 reset v thr selected rst threshold mlf pinstrapping before ss see table 7 v thr hyst rst hysteresis (2) 2% v rst rst open collector output v in > v inh and v fb < v th 4 ma sinking load 0.4 v 2 < v in < v inh 4 ma sinking load 0.8 delay v thd rst open collector released as soon as v delay > v thd v fb > v thr 1.19 1.23 4 1.25 8 v i d ch c delay charging current v fb > v thr 123 ? a table 5. electrical ch aracteristics (continued) symbol parameter test condition note min. typ. max. unit v pp g cs ?
docid026211 rev 3 11/63 a6986 electrical characteristics 63 all the population tested at t j = -40 to 135 c, v in = 12 v unless otherwise specified. all the population tested at t j = -40 to 135 c, v in = 12 v unless otherwise specified. thermal shutdown t shdwn thermal shutdown temperature (2) 165 c t hys thermal shutdown hysteresis (2) 30 1. parameter tested in static condition during testing phase. parameter value may change over dynamic application condition. 2. not tested in production. 3. lcm enables sleep mode at light load. 4. t j = -40 c. 5. measured at fsw = 250 khz. table 5. electrical ch aracteristics (continued) symbol parameter test condition note min. typ. max. unit table 6. f sw selection symbol r vcc (e24 series) r gnd (e24 series) f sw min. f sw typ. f sw max. note unit f sw 0 ? nc 225 250 275 (1) khz 1.8 k ? nc 285 (2) 3.3 k ? nc 330 5.6 k ? nc 380 10 k ? nc 435 nc 0 ? 450 500 550 (1) 18 k ? nc 575 (2) 33 k ? nc 660 56 k ? nc 755 nc 1.8 k ? 870 nc 3.3 k ? 900 1000 1100 nc 5.6 k ? 1150 (2) nc 10 k ? 1310 nc 18 k ? 1500 nc 33 k ? 1575 1750 1925 nc 56 k ? 1800 2000 2200 1. preferred codifications don't r equire any external resistor. 2. not tested in production.
electrical characteristics a6986 12/63 docid026211 rev 3 . v rst = 0.791 v typical, lnm and lcm preferred codifications don't require any external resistor. table 7. lnm / lcm selection symbol r vcc (e24 series) r gnd (e24 series) operating mode v rst /v out (tgt value) v rst min. v rst typ. v rst max. unit v rst 0 ? nc lcm 93% 0.779 0.791 0.802 v 8.2 k ? 1% nc 80% 0.670 0.680 0.690 18 k ? 1% nc 87% 0.728 0.740 0.751 39 k ? 1% nc 96% 0.804 0.816 0.828 nc 0 ? lnm 93% 0.779 0.791 0.802 nc 8.2 k ? 1% 80% 0.670 0.680 0.690 nc 18 k ? 1% 87% 0.728 0.740 0.751 nc 39 k ? 1% 96% 0.804 0.816 0.828
docid026211 rev 3 13/63 a6986 datasheet parameters over the temperature range 63 4 datasheet parameters ov er the temperature range the 100% of the population in the production flow is tested at three different ambient temperatures (-40 c, +25 c, +135 c) to gu arantee the datasheet parameters inside the junction temperature range (-40 c, +135 c). the device operation is guaranteed when the junction temperature is inside the (-40 c, +150 c) temperature range. the desi gner can estimate the s ilicon temperature increase respect to the ambient temperature evaluating the internal power losses generated during the device operation. however the embedded thermal protection disabl es the switching activity to protect the device in case the junction temperature reaches the t shtdwn (+165 c typ.) temperature. all the datasheet parameters can be guarant eed to a maximum junction temperature of +135 c to avoid triggering the thermal shutdown protection during the testing phase because of self-heating.
functional description a6986 14/63 docid026211 rev 3 5 functional description the a6986 device is based on a ?peak current mode?, constant frequency control. as a consequence, the intersection between the erro r amplifier output and the sensed inductor current generates the pwm control signal to drive the power switch. the device features lnm (low noise mode) th at is forced pwm control, or lcm (low consumption mode) to increase the efficiency at light load. the main internal blocks shown in the block diagram in figure 3 are: ? embedded power elements. thanks to the p-channel mosfet as high-side switch the device features low dropout operation ? a fully integrated sa wtooth oscillator with adjustable frequency ? a transconductance error amplifier ? the high-side current sense amplifier to sense the inductor current ? a ?pulse width modulator? (pwm) comparator and the driving circuitry of the embedded power elements ? the soft-start blocks to ramp the error ampl ifier reference voltage and so decreases the inrush current at power-up. the ss/inh pin inhibits the device when driven low. ? the switchover capability of the internal regu lator to supply a port ion of the quiescent current when the v bias pin is connected to an external output voltage ? the synchronization circuitry to manage master / slave operation and the synchronization to an external clock ? the current limitation circuit to implement the constant current protection, sensing pulse by pulse high-side / low-side switch current. in case of heavy short-circuit the current protection is fold back to decr ease the stress of the external components ? a circuit to implement the thermal protection function ? the ovp circuitry to discharge the output capacitor in case of overvoltage event ? mlf pin strapping sets the lnm/lcm mode and the thresholds of the rst comparator ? fsw pinstrapping sets the switching frequency ? the rst open collector output
docid026211 rev 3 15/63 a6986 functional description 63 figure 3. internal block diagram 5.1 power supply an d voltage reference the internal regulator block consists of a st art-up circuit, the voltage pre-regulator that provides current to all the blocks and the b andgap voltage reference. the starter supplies the startup current when the input voltage g oes high and the device is enabled (ss/inh pin over the inhibits threshold). the pre-regulator block supplies the bandgap cell and the rest of the circuitry with a regulated voltage that has a very low supply voltage noise sensitivity. switchover feature the switchover scheme of the pre-regulator block features to derive th e main contribution of the supply current for the internal circui try from an external voltage (3 v < v bias < 5.5 v is typically connected to the regulated output volt age). this helps to decrease the equivalent quiescent curren t seen at v in . (please refer to section 5.6: switchover feature on page 25 ). 5.2 voltages monitor an internal block continuously senses the v cc , v bias and v bg . if the monitored voltages are good, the regulator starts operating. there is also a hysteresis on the v cc (uvlo). 567 '5,9(5 *1' *1' 3($. &/ 9$ //(< &/ =(52 &5266,1* /223 &21752/ 26&,//$ 725 /1/& 5677+ /; )% ($ 32:(5 3 026 32:(5 1 026 6(16( 3 026 6(16( 1 026 9ff 6/23( 9,1 6<1& &203 *1' '5,9(5 *1' *1' 9$ //(< &/ /223 &21752/ ($ 6 026 293 0/) '(/$< '(/ $< 66,1+ 66,1+ 9 5() 7 66 )6: $0
functional description a6986 16/63 docid026211 rev 3 figure 4. internal circuit 5.3 soft-start and inhibit the soft-start and inhibit features are multiplexed on the same pin. an internal current source charges the external soft-start capacitor to implement a voltage ramp on the ss/inh pin. the device is inhibited as long as the ss/inh pin voltage is lower than the v inh threshold and the soft-start takes place when ss/inh pin crosses v ss start . (see figure 5: soft-start phase ). the internal current generator sources 1 ? a typ. current when the voltage of the vcc pin crosses the uvlo threshold. the current increases to 4 ? a typ. as soon as the ss/inh voltage is higher than the v inh threshold. this feature helps to decrease the current consumption in inhibit mode. an external open collector can be used to set the inhibit operation clamping the ss/inh voltage below v inh threshold. the startup feature minimizes the inrush current and decreases the stress of the power components during the power-up phase. the ramp implemented on the reference of the error amplifier has a gain three times higher (ss gain ) than the external ramp present at ss/inh pin. 67$57(5 ,&%,$6 35(5(*8/$725 %$1'*$3 95(* 95() ',1 9 &&
docid026211 rev 3 17/63 a6986 functional description 63 figure 5. soft-start phase the c ss is dimensioned accordingly with equation 1 : equation 1 where t ss is the soft-start time, i ss ch the charging current and v fb the reference of the error amplifier. the soft-start block supports the precharged output capacitor. c ss ss gain i ssch t ss ? v fb ------------------------------- - ? 3 4 ? at ss ? 0.85v --------------------------- ? ==
functional description a6986 18/63 docid026211 rev 3 figure 6. soft-start phase with precharged c out during normal operation a new soft-start cycle takes place in case of: ? thermal shutdown event ? uvlo event ? the device is driven in inh mode the soft-start capacitor is discharged with a 0. 6 ma typ. current cap ability for 1 msec time max. for complete and proper capacitor discharge in case of fault condition, a maximum c ss = 67 nf value is suggested. 5.3.1 ratiometric startup the ratiometric startup is implemented sharing t he same soft-start capacitor for a set of the a6986 device.
docid026211 rev 3 19/63 a6986 functional description 63 figure 7. ratiometric startup as a consequence all the internal current generators charge in parallel the external capacitor. the capacitor value is dimensioned accordingly with equation 2 : equation 2 where n a6986 represents the number of devices connected in parallel. for better tracking of the different output voltages the synchronization of the set of regulators is suggested. 9 287 9 287 9 287 w 9 $0 c ss n a6986 ss gain i ssch t ? ss v fb ------------------------------- - ? ? n a6986 3 4 ? at ss ? 0.85v --------------------------- ? ? ==
functional description a6986 20/63 docid026211 rev 3 figure 8. ratiometric startup operation 5.3.2 output voltage sequencing the a6986 device implements sequencing connect ing the rst pin of the master device to the ss/inh of the slave. the slave is inhibited as long as the master output voltage is outside regulation so implementing the sequencing (see figure 9 ).
docid026211 rev 3 21/63 a6986 functional description 63 figure 9. output voltage sequencing high flexibility is achieved thanks to the programmable rst thresholds (see table 7: lnm / lcm selection on page 12 ) and programmable delay time. to minimize the component count the delay pin capacitor can be also omitted so the pin works as a normal power good. 5.4 error amplifier the voltage error amplifier is the core of the loop regulation. it is a transconductance operational amplifier whose no n inverting input is connected to the internal voltage reference (0.85 v), while the inverting input (fb) is connected to the external divider or directly to the output voltage. the error amplifier output is compared with the inductor current sense information to perform pwm control. the error amplifier also determines the burst operation at light load when the lcm is active. 5.5 light load operation the mlf pinstrapping during the power-up phase determines the light load operation (refer to table 7: lnm / lcm selection on page 12 ). 9 287 9 287 9 287 w 9 w '(/$< w '(/$< w '(/$< $0 table 8. uncompensated error amplifier characteristics description values transconductance 155 s low frequency gain 100 db
functional description a6986 22/63 docid026211 rev 3 5.5.1 low noise mode (lnm) the low noise mode implements a forced pwm operation over the different loading conditions. the lnm features a constant switching frequency to minimize the noise in the final application and a constant voltage ripple at fixed v in . the regulator in steady loading condition never skip pulses and it operates in continuous conduction mode (ccm) over the different loading conditions. figure 10. low noise mode operation typical applications for the lnm operation are car audio, sensors. 5.5.2 low consumption mode (lcm) the low consumption mode maximizes the efficien cy at light load. the regulator prevents the switching activity whenev er the switch peak current request is lower than the i skip threshold (700 ma typical). as a consequence the a6986 device works in bursts and it minimizes the quiescent current request in t he meantime between the switching operation. the lcm operation satisfies the requirements of the unswitched car body applications (kl30). these applications are directly connected to the battery and are operating when the engine is disabled. the typical load when t he car is parked is represented by a can transceiver and a microcontroller in sleep mode (total load is around 20 - 30 a). as soon as the transceiver recognizes a valid word in the bus, it awakes the c and the rest of the application. the typical input current request of the module when the car is parked is 100 a typ. to prevent the battery discharge over the parking time. in order to minimize the regulator quiescent current re quest from the input voltage, the v bias pin can be connected to an
docid026211 rev 3 23/63 a6986 functional description 63 external voltage source in the range 3 v < v bias < 5.5 v (see chapter 5.1: power supply and voltage reference on page 15 ). in case the v bias pin is connected to the regulated output voltage (vout), the total current drawn from the input voltage can be calculated as: figure 11. lcm operation at zero load given the energy stored in the inductor during a burst, the voltage ripple depends on the capacitor value: equation 3 v out ripple ? q il c out ------------- - i l t ?? dt ? ?? 0 t burst ? c out ------------------------------------------- - ==
functional description a6986 24/63 docid026211 rev 3 figure 12. lcm operation over loading condition (part 1) figure 13. lcm operation over loading condition (part 2)
docid026211 rev 3 25/63 a6986 functional description 63 figure 14. the regulator works in ccm 5.6 switchover feature the switchover maximizes the efficiency at light load that is crucia l for lcm applications. 5.6.1 lcm the lcm operation satisfies the high efficiency requirements of the battery powered applications. in order to minimize the regula tor quiescent current request from the input voltage, the v bias pin can be connected to an external voltage source in the range 3 v < v bias < 5.5 v (see section 5.1: power supply and voltage reference on page 15 ). in case the v bias pin is connected to the regulated output voltage (v out ), the total current drawn from the input voltage can be calculated as: equation 4 where iq op v in , iq op v bias are defined in table 5: electrical characteristics on page 8 and ? a6986 is the efficiency of the conversion in the working point. 5.6.2 lnm equation 4 is also valid when the device works in lnm and it can increase the efficiency at medium load since the regulator always operates in continuous conduction mode. i qvin i qopvin 1 ? a6986 ----------------- v bias v in --------------- i qopvbias ? ? + =
functional description a6986 26/63 docid026211 rev 3 5.7 overcurrent protection the current protection circuitry features a cons tant current protection, so the device limits the maximum peak current (see table 5: electrical characteristics on page 8 ) in overcurrent condition. the a6986 device implements a pulse by pulse current sensing on both power elements (high-side and low-side switches) for effective current prot ection over the duty cycle range. the high-side current sensing is called ?peak? the low-side sensing ?valley?. the internal noise generated during the swit ching activity makes the current sensing circuitry ineffective for a mini mum conduction time of the power element. this time is called ?masking time? because the information from th e analog circuitry is masked by the logic to prevent an erroneous detection of the overcurrent event. as a consequence, the peak current protection is disabled for a masking ti me after the high-side switch is turned on, the valley for a masking time after the low-side swit ch is turned on. in other words, the peak current protection can be ineffective at ex tremely low duty cycle s, the valley current protection at extremely high duty cycles. the a6986 device assures an effective overcurrent protection sensing the current flowing in both power elements. in case one of the two cu rrent sensing circuitry is ineffective because of the masking time, the device is protected sensing the current on the opposite switch. thus, the combination of the ?peak? and ?valle y? current limits assure the effectiveness of the overcurrent protection even in extreme duty cycle conditions. the valley current threshold is designed higher than the peak to guarantee a proper operation. in case the current diverges becau se of the high-side masking time, the low-side power element is turned on until the switch current level drops below the valley current sense threshold. the low-side operation is able to prevent the high-side turn on, so the device can skip pulses decrea sing the swathing frequency.
docid026211 rev 3 27/63 a6986 functional description 63 figure 15. valley current sense operation in overcurrent condition figure 15 shows the switching frequency reduction during the valley current sense operation in case of extremely low duty cycle (v in 38 v, f sw = 500 khz short-circuit condition). in worst case scenario (like figure 15 ) of the overcurrent protection the switch current is limited to: equation 5 where i valley_th is the current threshold of the valley sensing circuitry (see table 5: electrical characteristics on page 8 ) and t mask_hs is the masking time of the high-side switch 100 nsec. typ.). in most of the overcurrent conditions the conduc tion time of the high-side switch is higher than the masking time and so the peak cu rrent protection limits the switch current. equation 6 i max = i peak_th i max i valleyth v in v out ? l ----------------------------- - t maskhs ? + =
functional description a6986 28/63 docid026211 rev 3 figure 16. peak current sense operation in overcurrent condition the dc current flowing in the load in overcurrent condition is: equation 7 ocp and switchover feature output capacitor discharging the current flowing to ground during heavy short-circuit events is only limited by parasitic elements like the output capacitor esr and short-circuit impedance. due to parasitic inductance of the short-circuit impedance, negative output voltage oscillations can be generated with hu ge discharging current levels (see figure 17 ). i dcoc v out ?? i max i ripple v out ?? 2 --------------------------------------- - ? i max v in v out ? 2l ? ----------------------------- - t on ? ?? ?? ? ==
docid026211 rev 3 29/63 a6986 functional description 63 figure 17. output voltage oscillations during heavy short-circuit figure 18. zoomed waveform the v bias pin absolute maximum ratings (see table 2: absolute maximum ratings on page 6 ) must be satisfied over the different dynamic conditions. if v bias is connected to gnd there are no issues (see figure 17 and figure 18 ). short-circuit current regulated output voltage inductor current switching node short-circuit current regulated output voltage inductor current switching node
functional description a6986 30/63 docid026211 rev 3 a small resistor value (few ohms) in series with v bias can help to limit the pin negative voltage (see figure 19 ) during heavy short-circuit events if it is connected to the regulated output voltage. figure 19. v bias in heavy short-circuit event 5.8 overvoltage protection the overvoltage protection monitors the fb pin and enables the low-side mosfet to discharge the output capacitor if the out put voltage is 20% over the nominal value. this is a second level protection and sh ould never be triggered in normal operating conditions if the system is properly dimens ioned. in other words, the selection of the external power components and the dynamic pe rformance determined by the compensation network should guarantee an output voltage regulation within the overvoltage threshold even during the worst case scenario in term of load transitions. the protection is reliable and also able to op erate even during normal load transitions for a system whose dynamic performance is not in line with the load dynamic request. as a consequence the output voltage regulation would be affected. figure 20 shows the overvoltage operation during a negative steep load transient for a system designed with huge inductor value and sm all output capacitor. the inductor value limits the switch current slew rate and the extr a charge flowing into th e small capacitor value generates an overvoltage event. this can be considered as an example for a system with dynamic performance not in line with the load request. the a6986 device implements a 1 a typ. negat ive current limitation to limit the maximum reversed switch current during the overvoltage operation. v bias pin voltage regulated output voltage inductor current switching node (purple) (cyan)
docid026211 rev 3 31/63 a6986 functional description 63 figure 20. overvoltage operation 5.9 thermal shutdown the shutdown block disables the switching activity if the junction temperature is higher than a fixed internal threshold (165 c typical). the thermal sensing element is close to the power elements, ensuring fast and accurate temperature detection . a hysteresis of approximately 30 c prevents the device from turning on and off continuously. when the thermal protection runs away a new soft-start cycle will take place.
closing the loop a6986 32/63 docid026211 rev 3 6 closing the loop figure 21. block diagram of the loop 6.1 g co (s) control to output transfer function the accurate control to output transfer function for a buck peak current mode converter can be written as: equation 8 where r load represents the load resistance, r i the equivalent sensing resistor of the current sense circuitry, ? ? p the single pole introduced by the the power stage and ? z the zero given by the esr of the output capacitor. f h (s) accounts the sampling effect performed by the pwm comparator on the output of the error amplifier that introduces a double pole at one half of the switching frequency. 9 ,1 5hvlvwruglylghu /&ilowhu 9 5() (uurudpsolilhu )% &rpshqvdwlrq qhwzrun 3:0frpsdudwru +6 vz lwfk 5 5 / & 287 & 3 5 & & & 3:0frqwuro &xuuhqwvhqvh /6 vz lwfk , +6 j &6 5 /2$' $0 g co s ?? r load r i ----------------- - 1 1 r load t sw ? l ----------------------------------- m c 1d ? ?? ? 0.5 ? ?? ? + ------------------------------------------------------------------------------------------------------- - 1 s ? z ------ + ?? ?? 1 s ? p ------ + ?? ?? --------------------- - f h ? s ?? ? ? =
docid026211 rev 3 33/63 a6986 closing the loop 63 equation 9 equation 10 where: equation 11 s n represents the on time slope of the sensed inductor current, s e the on time slope of the external ramp (v pp peak-to - peak amplitude) that implements the slope compensation to avoid sub-harmonic oscillation s at duty cycle over 50%. s e can be calculated from the parameter v pp ?? g cs given in table 5 on page 8 . the sampling effect contribution f h (s) is: equation 12 where: equation 13 ? z 1 esr c out ? --------------------------------- = ? p 1 r load c out ? -------------------------------------- - m c 1d ? ?? ? 0.5 ? lc out f sw ? ? ---------------------------------------------- + = m c 1 s e s n ------ + = s e v pp g cs f sw ?? = s n v in v out ? l ---------------------------- - = ? ? ? ? ? ? ? ? f h s ?? 1 1 s ? n q p ? ------------------- - s 2 ? n 2 --------- ++ ---------------------------------------------- = q p 1 ? m c 1d ? ?? 0.5 ? ? ?? ? ----------------------------------------------------------- - =
closing the loop a6986 34/63 docid026211 rev 3 6.2 error amplifier compensation network the typical compensation network require d to stabilize the system is shown in figure 22 . figure 22. transconductance embedded error amplifier r c and c c introduce a pole and a zero in the open loop gain. c p does not significantly affect system stability but it is useful to reduce th e noise at the output of the error amplifier. the transfer function of the error amplifier and its compensation network is: equation 14 where a vo = g m r o the poles of this transfer function are (if c c >> c 0 + c p ): equation 15 & 3 5 & & & )% &203 g9 5 * p g9 9 ($ 5 & & & & 3 & 95() 9 $0 a 0 s ?? a v0 1sr c c c ? ? + ?? ? s 2 r 0 c 0 c p + ?? ? r c c c sr 0 c c r 0 c 0 c p + ?? ? + ? r c c c ? + ?? 1 + ? + ? ? ? ------------------------------------------------------------------------------------------------------------------------------- -------------------------------------------------------------------- = f plf 1 2 ? r 0 c c ? ? ? ------------------------------------- =
docid026211 rev 3 35/63 a6986 closing the loop 63 equation 16 whereas the zero is defined as: equation 17 6.3 voltage divider the contribution of a simple voltage divider is: equation 18 a small signal capacitor in para llel to the upper resistor (see figure 23 ) of the voltage divider implements a leading network (f zero < f pole ), sometimes necessary to improve the system phase margin: figure 23. leading network example laplace transformer of the leading network: equation 19 f phf 1 2 ? r 0 c 0 c p + ?? ? ? ? -------------------------------------------------------- = f z 1 2 ? r c c c ? ? ? ------------------------------------- = g div s ?? r 2 r 1 r 2 + -------------------- = vljqdo*1' 3:5jqg 3:5jqg 9287 $ 9%,$6 567 9&& 66,1+ 6<1&+ )6: 0/) &203 '(/$< )% 6*1' 3*1' 3*1' /; /; 9,1 (3 5 &s *1' *1' &u 5 &f 9,1 5f $09 g div s ?? r 2 r 1 r 2 + -------------------- 1sr 1 c r1 ? ++ ?? 1s r 1 r 2 ? r 1 r 2 + -------------------- ? c r1 ? + ?? ?? ------------------------------------------------------------- ? =
closing the loop a6986 36/63 docid026211 rev 3 where: equation 20 6.4 total loop gain in summary, the open loop gain can be expressed as: equation 21 example 1 v in = 12 v, v out = 3.3 v, r out = 2.2 ? selecting l = 6.8 h, c out = 15 f and esr = 1 m ? , r c = 68 k ? , c c = 180 pf, c p = 6.8 pf (please refer to example 2 ), the gain and phase bode diagrams are plotted respectively in figure 24 and figure 25 . f z 1 2 ? r 1 c r1 ? ? ? ----------------------------------------- = f p 1 2 ? r 1 r ? 2 r 1 r 2 + -------------------- c r1 ? ? ? ------------------------------------------------------- = f z f p ? ?? g div s ?? g co s ?? a 0 s ?? ?? =
docid026211 rev 3 37/63 a6986 closing the loop 63 figure 24. module plot equation 22 [ [ [ [ [ (;7(51$//22302'8/( )uhtxhqf\>+]@ 0rgxoh>g%@ $0 bw 67khz = phase margin 53 0 =
closing the loop a6986 38/63 docid026211 rev 3 figure 25. phase plot the blue solid trace represents the transfer function including the sampling effect term (see equation 12 on page 33 ), the dotted blue trace neglects the contribution. 6.5 compensation network design the maximum bandwidth of the system can be designed up to f sw /6 to guarantee a valid small signal model. equation 23 equation 24 where: equation 25 [ [ [ [ [ (;7(51$//223*$,13+$6( $0 bw f sw 6 -------- - = r c 2 ? bw c out v out ?? ? ? 0.85v g cs g m typ ?? --------------------------------------------------------------- - = f pole ? p 2 ? ? ---------- - =
docid026211 rev 3 39/63 a6986 closing the loop 63 ? p is defined by equation 10 on page 33 , g cs represents the current sense transconductance (see table 5: electrical characteristics on page 8 ) and g m typ the error amplifier transconductance. equation 26 example 2 considering v in = 12 v, v out = 3.3 v, l = 6.8 ? h, c out = 15 ? f, f sw = 500 khz. the maximum system bandwidth is 80 khz. assuming to design the compensation network to achieve a system bandwidth of 70 khz: equation 27 equation 28 so accordingly with equation 24 and equation 26 : equation 29 equation 30 c c 5 2 ? r c bw ?? ? ------------------------------------- - = f pole 6khz = r load v out i out -------------- 2.2 ? == r c 68k ? = c c 168pf 180pf ? =
application notes a6986 40/63 docid026211 rev 3 7 application notes 7.1 output voltage adjustment the error amplifier reference voltage is 0.85 v typical. the output voltage is adjusted accordingly with equation 31 (see figure 26 ): equation 31 c r1 capacitor is sometimes useful to increase the small signal phase margin (please refer to section 6.5: compensation network design ). figure 26. a6986 application circuit 7.2 switching frequency a resistor connected to the fsw pin features the selection of the switching frequency. the pinstrapping is performed at power-up, before the soft-start takes place. the fsw pin is pinstrapped and then driven floating in order to minimize the quiescent current from vin. please refer to table 6: f sw selection on page 11 to identify the pull-up / pull-down resistor value. f sw = 250 khz / f sw = 500 khz preferred codifications don't require any external resistor. 7.3 mlf pin a resistor connected to the mlf pin features the selection of the between low noise mode / low consumption mode and the different rst thresholds. the pinstrapping is performed at power-up, before the soft-start takes place. the fsw pin is pinstrapped and then driven floating in order to minimize the quiescent cu rrent from vin. v out 0.85 1 r 1 r 2 ------ - + ?? ?? ? = vljqdo*1' 3:5jqg 3:5jqg 9287 $ 9%,$6 567 9&& 66,1+ 6<1&+ )6: 0/) &203 '(/$< )% 6*1' 3*1' 3*1' /; /; 9,1 (3 5 &s *1' *1' &u 5 &f 9,1 5f $09
docid026211 rev 3 41/63 a6986 application notes 63 please refer to table 7: lnm / lcm selection on page 12 to identify the pull-up / pull-down resistor value. (lnm, rst threshold 93%) / (lcm, rst threshold 93%) preferred codifications don't require any external resistor. 7.4 voltage supervisor the embedded voltage supervisor (composed of the rst and the delay pins) monitors the regulated output voltage and keeps the rst open collector output in low impedance as long as the v out is out of regulation. in order to ensure a proper reset of digital devices with a valid power supply, the device can delay the rst assertion with a programmable time. figure 27. voltage supervisor operation the comparator monitoring the fb voltage has four different programmable thresholds (80%, 87%, 93%, 96% nominal output voltage) for high flexibility (see section 7.3: mlf pin and table 7: lnm / lcm selection on page 12 ). when the rst comparator detects the output voltage is in regulation, a 2 ? a internal current source starts to charge an external capacitor to implement a voltage ramp on the delay pin. the rst open collector is then released as soon as v delay = 1.234 v (see figure 27 ). the cdelay is dimensioned accordingly with equation 32 : equation 32 the maximum suggested capacitor value is 270 nf. c delay i ssch t delay ? v delay ----------------------------------------- - 2 ? at delay ? 1.234v ------------------------------------- ==
application notes a6986 42/63 docid026211 rev 3 7.5 synchronization (lnm) beating frequency noise is an issue when multiple switching regulators populate the same application board. the a6986 synchronization circuitry features the same switching frequency for a set of regulators simply conn ecting their synch pin together, so preventing beating noise. the master device provides the synchronization signal to the others since the synch pin is i/o able to deliver or recognize a frequency signal. for proper synchronization of multiple regulators, all of them have to be configured with the same switching frequency (see table 6 on page 11 ), so the same resistor connected at the fsw pin. in order to minimize the rms current flowing through the input filter, the a6986 device provides a phase shift of 180 between t he master and the sla ves. if more than two devices are synchronized, all slaves will have a common 180 phase shift with respect to the master. considering two synchronized a6986 which regulates the same output voltage (i.e. operating with the same duty cycle), the inpu t filter rms current is optimized and is calculated as: equation 33 i rms i out 2 ----------- - 2d 1 2d ? ?? ? if d < 0.5 ? i out 2 ----------- - 2d 1 ? ?? 22d ? ?? ? if d > 0.5 ? ? ? ? ? ? ? ? =
docid026211 rev 3 43/63 a6986 application notes 63 figure 28 shows two regulators not synchronized. figure 28. two regulators not synchronized
application notes a6986 44/63 docid026211 rev 3 figure 29 shows the same regulators working synchronized. the master regulator (lx2 trace) delivers the synchronization signal (synch1, synch2 pins are connected together) to the slave device (lx1). the slave regula tor works in phase with the synchronization signal which is out of phase wit h the master switching operation. figure 29. two regulators synchronized multiple a6986 can be synchronized to an external frequency signal fed to the synch pin. in this case the set is phased to the refere nce and all the devices will work with 0 phase shift. since the slope compensation contribution, that is required to prevent subharmonic oscillations in peak current mo de architecture, depends on th e switching frequency, it is important to select the same switching frequency for all regulators (all of them operate as slave) one step lower than the reference signal (please refer to table 6: f sw selection on page 11 ). as a consequence, all the regulators have the same resistor connected to the fsw pin. the graphical representation of the input rms curr ent of the input filter in the case of two devices with 0 phase shift (synchronized to an external signal) or 180 phase shift (synchronized connecting their synch pins) re gulating the same output voltage is provided in figure 30 . to dimension the proper inpu t capacitor please refer to chapter 7.6.1: input capacitor selection .
docid026211 rev 3 45/63 a6986 application notes 63 figure 30. input rms current 7.6 design of the power components 7.6.1 input capacitor selection the input capacitor voltage rating must be higher than the maximum input operating voltage of the application. during the switching activity a pulsed current flows into the input capacitor and so its rms current capability must be se lected accordingly with the application conditions. internal losses of the input filter depends on the esr value so usually low esr capacitors (like multilayer ce ramic capacitors) have higher rm s current capability. on the other hand, given the rms current value, lowe r esr input filter has lower losses and so contributes to higher conversion efficiency. the maximum rms input current flowing through the capacitor can be calculated as: equation 34 where i out is the maximum dc output current, d is the duty cycles, ? is the efficiency. this function has a maximum at d = 0.5 and, considering ? = 1, it is equal to io/2. 506fxuuhqwqrupdol]hg,upv,287 wzr uhjxodwruv rshudwlqj lq skdvh wzr uhjxodwruv rshudwlqj rxw ri skdvh $09 'xw\f\foh i rms i out 1 d ? --- - ? ?? ?? d ? --- - ? ? =
application notes a6986 46/63 docid026211 rev 3 in a specific application the range of possible duty cycles has to be considered in order to find out the maximum rms input current. th e maximum and minimum duty cycles can be calculated as: equation 35 equation 36 where ? v high_side and ? v low_side are the voltage drops across the embedded switches. the peak to peak voltage across t he input filter can be calculated as: equation 37 in case of negligible esr (mlcc capacitor) the equation of cin as a function of the target vpp can be written as follows: equation 38 considering ?????? this function has its maximum in d = 0.5: equation 39 typically c in is dimensioned to keep the maximum peak-peak voltage across the input filter in the order of 5% v in_max . table 9. input capacitors manufacturer series size cap value ( ? f) rated voltage (v) tdk c3225x7s1h106m 1210 10 50 c3216x5r1h106m 1206 taiyo yuden umk325bj106mm-t 1210 d max v out ? v lowside + v inmin ? v lowside ? v highside ? + ------------------------------------------------------------------------------------------------ = d min v out ? v lowside + v inmax ? v lowside ? v highside ? + ------------------------------------------------------------------------------------------------- - = v pp i out c in f sw ? ------------------------ - 1 d ? --- - ? ?? ?? d ? --- - ? ? esr i out ? i l + ?? ? + = c in i out v pp f sw ? ------------------------- - 1 d ? --- - ? ?? ?? d ? --- - ? ? = c inmin i out 4v ppmax f sw ? ? ---------------------------------------------- =
docid026211 rev 3 47/63 a6986 application notes 63 7.6.2 inductor selection the inductor current ripple flowing into the ou tput capacitor determines the output voltage ripple (please refer to section 7.6.3 ). usually the inductor value is selected in order to keep the current ripple lower than 20% - 40% of the output current over the input voltage range. the inductance value can be calculated by equation 40 : equation 40 where t on and t off are the on and off time of the internal power switch. the maximum current ripple, at fixed v out, is obtained at maximum t off that is at minimum duty cycle (see section 7.6.1: input capacitor selection to calculate minimum duty). so fixing ? i l = 20% to 40% of the maximum output current, the minimum inductance value can be calculated: equation 41 where f sw is the switching frequency 1/(t on + t off ). for example for v out = 3.3 v, v in = 12 v, i o = 2 a and f sw = 500 khz the minimum inductance value to have ? i l = 30% of io is about 8.2 h. the peak current through the inductor is given by: equation 42 so if the inductor value decreases, the peak current (that has to be lower than the current limit of the device) increases. the higher is the inductor value, the higher is the average output current that can be delivered , without reaching the current limit. in table 10 some inductor part numbers are listed. 7.6.3 output capacitor selection the triangular shape current ripple (with zero average value) flowing into the output capacitor gives the output voltage ripple, that depends on the capacitor value and the equivalent resistive component (esr). as a consequence the output capacitor has to be selected in order to have a voltage ripple compliant with the application requirements. table 10. inductors manufacturer series inductor value ( ? h) saturation current (a) coilcraft xal50xx 2.2 to 22 6.5 to 2.7 xal60xx 2.2 to 22 12.5 to 4 ? i l v in v out ? l ----------------------------- - t on ? v out l -------------- t off ? == l min v out ? i lmax ------------------- 1d min ? f sw ---------------------- - ? = i lpk ? i out ? i l 2 -------- + =
application notes a6986 48/63 docid026211 rev 3 the voltage ripple equation can be calculated as: equation 43 usually the resistive component of the ripple can be neglected if the selected output capacitor is a multi layer ceramic capacitor (mlcc). the output capacitor is important also for loop stability: it determines the main pole and the zero due to its esr. (see section 6: closing the loop on page 32 to consider its effect in the system stability). for example with v out = 3.3 v, v in = 12 v, ? i l = 0.6 a, f sw = 500 khz (resulting by the inductor value) and c out = 10 ? f mlcc: equation 44 the output capacitor value has a key role to sustain the output voltage during a steep load transient. when the load transient slew ra te exceeds the system bandwidth, the output capacitor provides the current to the load. in case the final application specifies high slew rate load transient, th e system bandwidth must be maximi zed and the output capacitor has to sustain the output volta ge for time response shorter than the loop response time. in table 11 some capacitor series are listed. table 11. output capacitors manufacturer series cap value ( ? f) rated voltage (v) esr (m ? ) murata grm32 22 to 100 6.3 to 25 < 5 grm31 10 to 47 6.3 to 25 < 5 panasonic ecj 10 to 22 6.3 < 5 eefcd 10 to 68 6.3 15 to 55 sanyo tpa/b/c 100 to 470 4 to 16 40 to 80 tdk c3225 22 to 100 6.3 < 5 ? v out esr ? ? i lmax ? i lmax 8c out f sw ? ? --------------------------------------- + = ? v out v out ------------------ 1 v out -------------- ? i lmax c out f sw ? ------------------------------ ? ? 1 33 ------ 06 ? 810 ? f 500khz ? ? -------------------------------------------------- ? ?? ?? 15mv 3.3 --------------- - 0.45% ===
docid026211 rev 3 49/63 a6986 application board 63 8 application board the reference evaluation bo ard schematic is shown in figure 31 . figure 31. evaluation board schematic the additional input filter (c16, l3, c15, l2, c14) limits the conducted emission on the power supply. vljqdo*1' srzhu*1' 9 vl]h 9,1b)/7 3*1' 9,1b)/7 3*1' & x) & x) 5 5 73 6<1&+ 73 - - & s & s & x) 9 & x) 9 73 9,1b(0, 73 9,1b(0, / x+ / x+ & x) 9 & x) 9 5 5 & 10 & 10 5 10 5 10 & q) & q) & 10 & 10 5 0 5 0 & s & s - - 73 73 *1' 73 66,1+ 73 5 n 5 n 5 10 5 10 & 10 & 10 73 73 567 5 10 5 10 & x) 9 & x) 9 & 10 & x) & x) 5 5 5 n 5 n 5 5 8 / 8 / 567 9&& 66,1+ 6<1&+ )6: 0/) &203 '(/$< )% 6*1' 3*1' 3*1' /; /; 9,1 9%,$6 (3 73 *1' 73 *1' - - & 10 & 10 73 9287 73 & q) & q) / 10 / 10 73 9,1 73 9,1 5 n 5 n & q) & q) / x+ / x+ $0 a6986 table 12. bill of material reference part number description manufacturer c1 cga5l3x5r1h106k 10 ? f - 1206 - 50 v - x7r - 10% tdk c2 c2012x7s2a105k 1 ? f - 0805 - 50 v - x7s - 10% tdk c3 470 nf - 50 v - 0603 c4 2.2 pf - 50 v - 0603 c5 68 nf - 50 v - 0603 c6 10 nf - 50 v - 0603 c8 120 pf - 50 v - 0603 c1 cga5l3x5r1h106k 10 ? f - 1206 - 50 v - x7r - 10% tdk c9 c3216x5r1c476m 47 ? f - 1206 - 16 v - x5r - 20% tdk c14, c15, c16 c3216x7r1h475k160ac 4.7 ? f - 1206 - 50 v - x7r - 10% tdk c7, c10, c11, c13 not mounted r1, r4 0 r - 0603
application board a6986 50/63 docid026211 rev 3 figure 32 and figure 33 show the magnitude and phase margin bode?s plots related to the evaluation board presented in figure 31 . the small signal dynamic performance of the demonstration board is: equation 45 r6 1 m ? - 1%- 0603 r7 180 k ? - 1% - 0603 r8 130 k ? - 1% - 0603 r9 62 k ? - 1% - 0603 r11 10 ? - 1% - 0603 r2, r3, r5, r10 not mounted l1 xal5050-103mec 10 ? hcoilcraft l2 xal5030-472mec 4.7 ? hcoilcraft l3 mpz2012s221a emc bead tdk j1 open j2 open j3 closed switchover j4 open u1 a6986 stm table 12. bill of material (continued) reference part number description manufacturer bw 67khz = phase margin 53 0 =
docid026211 rev 3 51/63 a6986 application board 63 figure 32. magnitude bode?s plot figure 33. phase margin bode?s plot [ [ [ [ [ (;7(51$//22302'8/( )uhtxhqf\>+]@ 0rgxoh>g%@ $0 x [ [ [ [ (;7(51$//223*$,13+$6( )uhtxhqf\>+]@ 3kdvh $0
application board a6986 52/63 docid026211 rev 3 figure 34. top layer figure 35. bottom layer
docid026211 rev 3 53/63 a6986 efficiency curves 63 9 efficiency curves figure 36. efficiency curves over f sw : v in = 13.5 v - v out = 3.3 v figure 37. efficiency curves over f sw : v in = 13.5 v - v out = 3.3 v (log scale) 60 65 70 75 80 85 90 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 vin=13.5v vout=3.3v a6986 500khz vbias pskip vin=13.5v vout=3.3va6986 500khz novbias pskip vin=13.5v vout=3.3v a6986 500khz novbias nopskip vin=13.5v vout=3.3v a6986 500khz vbias nopskip vin=13.5v vout=3.3v 1mhz vbias pskip vin=13.5v vout=3.3v 1mhz novbias pskip vin=13.5v vout=3.3v 1mhz novbias nopskip vin=13.5v vout=3.3v 1mhz vbias nopskip vin=13.5v vout=3.3v 2mhz vbias nospkip vin=13.5v vout=3.3v 2mhz novbias nospkip vin=13.5v vout=3.3v 2mhz novbias spkip vin=13.5v vout=3.3v 2mhz vbias spkip 60 65 70 75 80 85 90 0.0015 0.015 0.15 vin=13.5v vout=3.3v a6986 500khz vbias pskip vin=13.5v vout=3.3va6986 500khz novbias pskip vin=13.5v vout=3.3v a6986 500khz novbias nopskip vin=13.5v vout=3.3v a6986 500khz vbias nopskip vin=13.5v vout=3.3v 1mhz vbias pskip vin=13.5v vout=3.3v 1mhz novbias pskip vin=13.5v vout=3.3v 1mhz novbias nopskip vin=13.5v vout=3.3v 1mhz vbias nopskip vin=13.5v vout=3.3v 2mhz vbias nospkip vin=13.5v vout=3.3v 2mhz novbias nospkip vin=13.5v vout=3.3v 2mhz novbias spkip vin=13.5v vout=3.3v 2mhz vbias spkip
efficiency curves a6986 54/63 docid026211 rev 3 figure 38. efficiency curves over f sw : v in = 13.5 v - v out = 5 v figure 39. efficiency curves over f sw : v in = 13.5 v - v out = 5 v (log scale) 60 65 70 75 80 85 90 95 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 vin=13.5v vout=5v a6986 500khz vbias nopskip vin=13.5v vout=5v a6986 500khz novbias nopskip vin=13.5v vout=5v a6986 500khz novbias pskip vin=13.5v vout=5v a6986 500khz vbias pskip vin=13.5v vout=5v 1mhz vbias nospkip vin=13.5v vout=5v 1mhz novbias nospkip vin=13.5v vout=5v 1mhz novbias spkip vin=13.5v vout=5v 1mhz vbias spkip vin=13.5v vout=5v 2mhz vbias spkip vin=13.5v vout=5v 2mhz novbias spkip vin=13.5v vout=5v 2mhz novbias nospkip vin=13.5v vout=5v 2mhz vbias nospkip 60 65 70 75 80 85 90 95 0.0015 0.015 0.15 vin=13.5v vout=5v a6986 500khz vbias nopskip vin=13.5v vout=5v a6986 500khz novbias nopskip vin=13.5v vout=5v a6986 500khz novbias pskip vin=13.5v vout=5v a6986 500khz vbias pskip vin=13.5v vout=5v 1mhz vbias nospkip vin=13.5v vout=5v 1mhz novbias nospkip vin=13.5v vout=5v 1mhz novbias spkip vin=13.5v vout=5v 1mhz vbias spkip vin=13.5v vout=5v 2mhz vbias spkip vin=13.5v vout=5v 2mhz novbias spkip vin=13.5v vout=5v 2mhz novbias nospkip vin=13.5v vout=5v 2mhz vbias nospkip
docid026211 rev 3 55/63 a6986 efficiency curves 63 figure 40. efficiency curves over f sw : v in = 24 v - v out = 3.3 v figure 41. efficiency curves over f sw : v in = 24 v - v out = 3.3 v (log scale) 50 55 60 65 70 75 80 85 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 vin=24v vout=3.3v a6986 500khz vbias pskip vin=24v vout=3.3v a6986 500khz novbias pskip vin=24v vout=3.3v a6986 500khz novbias nopskip vin=24v vout=3.3v a6986 500khz vbias nopskip vin=24v vout=3.3v 1mhz vbias pskip vin=24v vout=3.3v 1mhz novbias pskip vin=24v vout=3.3v 1mhz novbias nopskip vin=24v vout=3.3v 1mhz vbias nopskip vin=24v vout=3.3v 2mhz vbias nospkip vin=24v vout=3.3v 2mhz novbias nospkip vin=24v vout=3.3v 2mhz novbias spkip vin=24v vout=3.3v 2mhz vbias spkip 50 55 60 65 70 75 80 85 0.0025 0.025 0.25 vin=24v vout=3.3v a6986 500khz vbias pskip vin=24v vout=3.3v a6986 500khz novbias pskip vin=24v vout=3.3v a6986 500khz novbias nopskip vin=24v vout=3.3v a6986 500khz vbias nopskip vin=24v vout=3.3v 1mhz vbias pskip vin=24v vout=3.3v 1mhz novbias pskip vin=24v vout=3.3v 1mhz novbias nopskip vin=24v vout=3.3v 1mhz vbias nopskip vin=24v vout=3.3v 2mhz vbias nospkip vin=24v vout=3.3v 2mhz novbias nospkip vin=24v vout=3.3v 2mhz novbias spkip vin=24v vout=3.3v 2mhz vbias spkip
efficiency curves a6986 56/63 docid026211 rev 3 figure 42. efficiency curves over f sw : v in = 24 v - v out = 5 v figure 43. efficiency curves over f sw : v in = 24 v - v out = 5 v (log scale) 50 55 60 65 70 75 80 85 90 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 vin=24v vout=5v a6986 500khz vbias nopskip vin=24v vout=5v a6986 500khz novbias nopskip vin=24v vout=5v a6986 500khz novbias pskip vin=24v vout=5v a6986 500khz vbias pskip vin=24v vout=5v 1mhz vbias nospkip vin=24v vout=5v 1mhz novbias nospkip vin=24v vout=5v 1mhz novbias spkip vin=24v vout=5v 1mhz vbias spkip vin=24v vout=5v 2mhz vbias spkip vin=24v vout=5v 2mhz novbias spkip vin=24v vout=5v 2mhz novbias nospkip vin=24v vout=5v 2mhz vbias nospkip 50 55 60 65 70 75 80 85 90 0.0025 0.025 0.25 vin=24v vout=5v a6986 500khz vbias nopskip vin=24v vout=5v a6986 500khz novbias nopskip vin=24v vout=5v a6986 500khz novbias pskip vin=24v vout=5v a6986 500khz vbias pskip vin=24v vout=5v 1mhz vbias nospkip vin=24v vout=5v 1mhz novbias nospkip vin=24v vout=5v 1mhz novbias spkip vin=24v vout=5v 1mhz vbias spkip vin=24v vout=5v 2mhz vbias spkip vin=24v vout=5v 2mhz novbias spkip vin=24v vout=5v 2mhz novbias nospkip vin=24v vout=5v 2mhz vbias nospkip
docid026211 rev 3 57/63 a6986 efficiency curves 63 figure 44. efficiency curves: f sw = 500khz - v in = 24 v - v out = 3.3 v figure 45. efficiency curves: f sw = 500 khz - v in = 13.5 v - v out = 3.3 v (log scale) figure 46. efficiency curves: f sw = 500 khz - v in = 13.5 v - v out = 5 v 60 65 70 75 80 85 90 95 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 vin=13.5v vout=3.3v a6986 500khz vbias pskip vin=13.5v vout=3.3v a6986 500khz novbias pskip vin=13.5v vout=3.3v a6986 500khz novbias nopskip vin=13.5v vout=3.3v a6986 500khz vbias nopskip 30 40 50 60 70 80 90 0.001 0.01 0.1 vin=13.5v vout=3.3v a6986 500khz vbias pskip vin=13.5v vout=3.3v a6986 500khz novbias pskip vin=13.5v vout=3.3v a6986 500khz novbias nopskip vin=13.5v vout=3.3v a6986 500khz vbias nopskip 55 60 65 70 75 80 85 90 95 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 vin=13.5v vout=5v a6986 500khz vbias nopskip vin=13.5v vout=5v a6986 500khz novbias nopskip vin=13.5v vout=5v a6986 500khz novbias pskip vin=13.5v vout=5v a6986 500khz vbias pskip
efficiency curves a6986 58/63 docid026211 rev 3 figure 47. efficiency curves: f sw = 500 khz - v in = 13.5 v - v out = 5 v (log scale) figure 48. efficiency curves: f sw = 500 khz - v in = 24 v - v out = 3.3 v figure 49. efficiency curves: f sw = 500 khz - v in = 24 v - v out = 3.3 v (log scale) 20 30 40 50 60 70 80 90 0.001 0.01 0.1 vin=13.5v vout=5v a6986 500khz vbias nopskip vin=13.5v vout=5v a6986 500khz novbias nopskip vin=13.5v vout=5v a6986 500khz novbias pskip vin=13.5v vout=5v a6986 500khz vbias pskip 50 55 60 65 70 75 80 85 90 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 vin=24v vout=3.3v a6986 500khz vbias pskip vin=24v vout=3.3v a6986 500khz novbias pskip vin=24v vout=3.3v a6986 500khz novbias nopskip vin=24v vout=3.3v a6986 500khz vbias nopskip 20 30 40 50 60 70 80 0.001 0.01 0.1 vin=24v vout=3.3v a6986 500khz vbias pskip vin=24v vout=3.3v a6986 500khz novbias pskip vin=24v vout=3.3v a6986 500khz novbias nopskip vin=24v vout=3.3v a6986 500khz vbias nopskip
docid026211 rev 3 59/63 a6986 efficiency curves 63 figure 50. efficiency curves: f sw = 500 khz - v in = 24 v - v out = 5 v (log scale) figure 51. efficiency curves: f sw = 500 khz - v in = 24 v - v out = 5 v (log scale) 45 50 55 60 65 70 75 80 85 90 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 vin=24v vout=5v a6986 500khz vbias nopskip vin=24v vout=5v a6986 500khz novbias nopskip vin=24v vout=5v a6986 500khz novbias pskip vin=24v vout=5v a6986 500khz vbias pskip 20 30 40 50 60 70 80 90 0.001 0.01 0.1 vin=13.5v vout=5v a6986 500khz vbias nopskip vin=13.5v vout=5v a6986 500khz novbias nopskip vin=13.5v vout=5v a6986 500khz novbias pskip vin=13.5v vout=5v a6986 500khz vbias pskip
package information a6986 60/63 docid026211 rev 3 10 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions a nd product status are available at: www.st.com . ecopack is an st trademark.
docid026211 rev 3 61/63 a6986 package information 63 figure 52. htssop16 package outline . table 13. htssop16 package mechanical data symbol dimensions (mm) min. typ. max. a 1.20 a1 0.15 a2 0.80 1.00 1.05 b 0.19 0.30 c 0.09 0.20 d 4.90 5.00 5.10 d1 2.8 3 3.2 e 6.20 6.40 6.60 e1 4.30 4.40 4.50 e2 2.8 3 3.2 e0.65 l 0.45 0.60 0.75 l1 1.00 k 0.00 8.00 aaa 0.10
order codes a6986 62/63 docid026211 rev 3 11 order codes 12 revision history table 14. order codes part numbers package packaging a6986 htssop16 tube A6986TR tape and reel table 15. document revision history date revision changes 24-apr-2014 1 initial release. 12-may-2014 2 updated the document status from ?preliminary? to ?production data? on page 1. updated section 2.3: maximum ratings on page 6 (added text above table 2 ). updated section 2.5: esd protection on page 7 (updated value of ?mm? test condition in table 4 ). 22-aug-2014 3 updated section : features on page 1 (replaced 5 by 8 ? a i q- shtdwn ). updated section 4: datasheet parameters over the temperature range on page 13 (updated junction temperature 150 c min. to 165 c typ.). updated equation 7 on page 28 , equation 8 on page 32 , equation 10 on page 33 , equation 24 on page 38 , equation 34 on page 45 , equation 37 on page 46 to equation 39 on page 46 , equation 41 on page 47 to equation 44 on page 48 . updated section 6.1: g co (s) control to output transfer function on page 32 (replaced ?r 0 ? by ?r load ? and ?lc filter? by ?power stage?). updated figure 21 on page 32 , figure 22 on page 34 , and figure 30 on page 45 . added section 9: efficiency curves on page 53 .
docid026211 rev 3 63/63 a6986 63 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

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